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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:16:05 08/12/2015 
-- Design Name: 
-- Module Name:    counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           en  : in  STD_LOGIC;
           cnt : out STD_LOGIC_VECTOR (31 downto 0));
end counter;

architecture Behavioral of counter is
	signal cnt_signal : STD_LOGIC_VECTOR (31 downto 0);
begin

process(clk, clr)
begin
	if (clr = '1') then
		cnt_signal <= (others => '0');
	elsif (clk'event and clk='1' and en='1' and clr='0') then
		cnt_signal <= cnt_signal + 1;
		--cnt<=conv_std_logic_vector(cnt_signal,32);
	end if;
end process;

cnt <= cnt_signal;

end Behavioral;

